High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References

Junyi Yang; Shuai Dong; Zhengnan Fu; Hongyang Shang; Arindam Basu

doi:10.1109/DAC63849.2025.11133014

High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References

Junyi Yang^* (Co-first Author), Shuai Dong (Co-first Author), Zhengnan Fu, Hongyang Shang, Arindam Basu^*

^*Corresponding author for this work

Department of Electrical Engineering

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Abstract

This article proposes a 256 × 128 in-memory computing array using reconfigurable in-memory analog-to-digital conversion with shared references for high area efficiency (area overhead of 3% is 9X better than traditional). A dual-8T SRAM bitcell is used to achieve read-write decoupling and store ternary weights. Read World Line Under Drive enabled Cascode helps to minimize current variations producing high linearity. Multi-bit input is handled with low latency and high energy-efficiency by using bit-slicing (BS) with near-memory charge-sharing based binary weighted accumulator (CHA). Using noise resilient training, we show software comparable performance for a MLP on MNIST, VGG-8 on CIFAR-10, and graph attention network on Cora, with respective accuracy reductions of only 0.1%, 0.8% and 0.5% due to non-idealities. The proposed macro demonstrates high energy/area efficiency (1146 TOPS/W, 27 TOPS/mm² at 1/2/1b) in 65nm CMOS. It increases throughput (by 1.9X) and linearity (by 23X) compared to input pulse-width modulation by using BS and CHA. Compared to conventional BS with digital accumulation after ADC, this method has 1.7X/6.6X better energy-efficiency/throughput by reducing ADC operations. © 2025 IEEE.

Original language	English
Title of host publication	2025 62nd ACM/IEEE Design Automation Conference (DAC)
Publisher	IEEE
Number of pages	7
ISBN (Electronic)	979-8-3315-0304-8
DOIs	https://doi.org/10.1109/DAC63849.2025.11133014
Publication status	Published - 2025
Event	62nd ACM/IEEE Design Automation Conference, DAC 2025 - San Francisco, United States Duration: 22 Jun 2025 → 25 Jun 2025

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	62nd ACM/IEEE Design Automation Conference, DAC 2025
Place	United States
City	San Francisco
Period	22/06/25 → 25/06/25

Funding

This work was supported by the Innovation Technology Fund Mid-Stream Research Program (ITF MSRP) under Grant ITS/018/22MS. Any opinions, findings, conclusions, or recommendations expressed in this material do not reflect the views of the Government of the Hong Kong Special Administrative Region, the Innovation and Technology Commission, or the Innovation and Technology Fund Research Projects Assessment Panel. (Junyi Yang and Shuai Dong contributed equally to this work.)

Research Keywords

Charge-sharing
In-memory ADC
In-memory computing
Multi-bit
SRAM

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/DAC63849.2025.11133014

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Cite this

@inproceedings{c8a44f52196f4d4d949544f4b9bf9ea9,

title = "High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References",

abstract = "This article proposes a 256 × 128 in-memory computing array using reconfigurable in-memory analog-to-digital conversion with shared references for high area efficiency (area overhead of 3% is 9X better than traditional). A dual-8T SRAM bitcell is used to achieve read-write decoupling and store ternary weights. Read World Line Under Drive enabled Cascode helps to minimize current variations producing high linearity. Multi-bit input is handled with low latency and high energy-efficiency by using bit-slicing (BS) with near-memory charge-sharing based binary weighted accumulator (CHA). Using noise resilient training, we show software comparable performance for a MLP on MNIST, VGG-8 on CIFAR-10, and graph attention network on Cora, with respective accuracy reductions of only 0.1%, 0.8% and 0.5% due to non-idealities. The proposed macro demonstrates high energy/area efficiency (1146 TOPS/W, 27 TOPS/mm2 at 1/2/1b) in 65nm CMOS. It increases throughput (by 1.9X) and linearity (by 23X) compared to input pulse-width modulation by using BS and CHA. Compared to conventional BS with digital accumulation after ADC, this method has 1.7X/6.6X better energy-efficiency/throughput by reducing ADC operations. {\textcopyright} 2025 IEEE.",

keywords = "Charge-sharing, In-memory ADC, In-memory computing, Multi-bit, SRAM",

author = "Junyi Yang and Shuai Dong and Zhengnan Fu and Hongyang Shang and Arindam Basu",

year = "2025",

doi = "10.1109/DAC63849.2025.11133014",

language = "English",

series = "Proceedings - Design Automation Conference",

publisher = "IEEE",

booktitle = "2025 62nd ACM/IEEE Design Automation Conference (DAC)",

address = "United States",

note = "62nd ACM/IEEE Design Automation Conference, DAC 2025 ; Conference date: 22-06-2025 Through 25-06-2025",

}

Yang, J , Dong, S , Fu, Z , Shang, H & Basu, A 2025, High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References. in 2025 62nd ACM/IEEE Design Automation Conference (DAC). Proceedings - Design Automation Conference, IEEE, 62nd ACM/IEEE Design Automation Conference, DAC 2025, San Francisco, United States, 22/06/25. https://doi.org/10.1109/DAC63849.2025.11133014

High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References. / Yang, Junyi (Co-first Author); Dong, Shuai (Co-first Author); Fu, Zhengnan et al.
2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025. (Proceedings - Design Automation Conference).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References

AU - Yang, Junyi

AU - Dong, Shuai

AU - Fu, Zhengnan

AU - Shang, Hongyang

AU - Basu, Arindam

PY - 2025

Y1 - 2025

N2 - This article proposes a 256 × 128 in-memory computing array using reconfigurable in-memory analog-to-digital conversion with shared references for high area efficiency (area overhead of 3% is 9X better than traditional). A dual-8T SRAM bitcell is used to achieve read-write decoupling and store ternary weights. Read World Line Under Drive enabled Cascode helps to minimize current variations producing high linearity. Multi-bit input is handled with low latency and high energy-efficiency by using bit-slicing (BS) with near-memory charge-sharing based binary weighted accumulator (CHA). Using noise resilient training, we show software comparable performance for a MLP on MNIST, VGG-8 on CIFAR-10, and graph attention network on Cora, with respective accuracy reductions of only 0.1%, 0.8% and 0.5% due to non-idealities. The proposed macro demonstrates high energy/area efficiency (1146 TOPS/W, 27 TOPS/mm2 at 1/2/1b) in 65nm CMOS. It increases throughput (by 1.9X) and linearity (by 23X) compared to input pulse-width modulation by using BS and CHA. Compared to conventional BS with digital accumulation after ADC, this method has 1.7X/6.6X better energy-efficiency/throughput by reducing ADC operations. © 2025 IEEE.

AB - This article proposes a 256 × 128 in-memory computing array using reconfigurable in-memory analog-to-digital conversion with shared references for high area efficiency (area overhead of 3% is 9X better than traditional). A dual-8T SRAM bitcell is used to achieve read-write decoupling and store ternary weights. Read World Line Under Drive enabled Cascode helps to minimize current variations producing high linearity. Multi-bit input is handled with low latency and high energy-efficiency by using bit-slicing (BS) with near-memory charge-sharing based binary weighted accumulator (CHA). Using noise resilient training, we show software comparable performance for a MLP on MNIST, VGG-8 on CIFAR-10, and graph attention network on Cora, with respective accuracy reductions of only 0.1%, 0.8% and 0.5% due to non-idealities. The proposed macro demonstrates high energy/area efficiency (1146 TOPS/W, 27 TOPS/mm2 at 1/2/1b) in 65nm CMOS. It increases throughput (by 1.9X) and linearity (by 23X) compared to input pulse-width modulation by using BS and CHA. Compared to conventional BS with digital accumulation after ADC, this method has 1.7X/6.6X better energy-efficiency/throughput by reducing ADC operations. © 2025 IEEE.

KW - Charge-sharing

KW - In-memory ADC

KW - In-memory computing

KW - Multi-bit

KW - SRAM

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DO - 10.1109/DAC63849.2025.11133014

M3 - RGC 32 - Refereed conference paper (with host publication)

T3 - Proceedings - Design Automation Conference

BT - 2025 62nd ACM/IEEE Design Automation Conference (DAC)

PB - IEEE

T2 - 62nd ACM/IEEE Design Automation Conference, DAC 2025

Y2 - 22 June 2025 through 25 June 2025

ER -

High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared References

Abstract

Publication series

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Funding

Research Keywords

UN SDGs

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