High efficiency power amplifier - Distributed amplifier topology and non-uniform load-pull (NLP) power combining technique

A high efficiency power amplifier (PA) is proposed by using distributed amplifier topology and non-uniform load-pull (NLP) power combining technique. The novel NLP power combining technique is proposed for distributed amplifier (DA) with different stages. This approach allows efficient distributed combining of field-effect transistors (FETs) output power without the use of multi-way power combiners. The proposed distributed amplifier's topology uses a quarter-wave short-circuit stub or open circuit to replace the drain line lossy dummy load. This topology is able to achieve power equalisation among the FETs at microwave frequencies. This design method ensures optimum loadlines are achieved for all FETs and the efficiency obtained is compared with the conventional single-transistor class-A power amplifier using the same FET type. Distributed amplifier with different stages has different optimum loadline resistance. The optimum characteristic impedance of the drain output transmission line presented here obtains the powermatched condition for all FETs. This NLP power combining technique is demonstrated at 2 GHz with 1-stage, 2-stage and 3-stage distributed amplifiers. Experimental results show that the power-added efficiency (PAE) of these three different distributed amplifiers is greater than 35% at the 1-dB gain compression point. The maximum efficiency is greater than 35% over a bandwidth of 10%. The 3-stage distributed amplifier demonstrates an output power level of 27.4 dBm at the 1-dB gain compression point with power combining efficiency (PCE) around 90%.