Hierarchical segmentation for hardware function evaluation

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

35 Scopus Citations
View graph of relations

Author(s)

Detail(s)

Original languageEnglish
Article number4689314
Pages (from-to)103-116
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number1
Publication statusPublished - Jan 2009
Externally publishedYes

Abstract

This paper presents a method for evaluating functions based on piecewise polynomial approximations (splines) with a hierarchical segmentation scheme targeting hardware implementation. The methodology provides significant reduction in table size compared to traditional uniform segmentation approaches. The use of hierarchies involving uniform splines and splines with size varying by powers of two is particularly well suited for the coverage of nonlinear regions. The segmentation step is automated and supports user-supplied precision requirements and approximation method. Bit-widths of the coefficients and arithmetic operators are optimized to minimize circuit area and enable a guarantee of 1 unit in the last place (ulp) accuracy at the output. A coefficient transformation technique is also described, which significantly reduces the dynamic ranges of the fixed-point polynomial coefficients. The hierarchical segmentation method is illustrated using a set of functions including -(x/2) log2x, cos-1(x), √- ln(x), a high-degree rational function, ln(1+x), and 1/(1+x). Various degree-1 and degree-2 approximation results for precisions between 8 to 24 bits are given. Hardware realizations are demonstrated on a Xilinx Virtex-4 field-programmable gate array (FPGA). © 2006 IEEE.

Research Area(s)

  • Circuit synthesis, Design automation, Digital systems, Field-programmable gate arrays (FPGAs), Piecewise poly nomial approximation

Citation Format(s)

Hierarchical segmentation for hardware function evaluation. / Lee, Dong-U; Cheung, Ray C. C.; Luk, Wayne; Villasenor, John D.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 1, 4689314, 01.2009, p. 103-116.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review