Hardware implementation of genetic algorithms using FPGA

Wallace Tang; Leslie Yip

doi:10.1109/MWSCAS.2004.1354049

Hardware implementation of genetic algorithms using FPGA

Wallace Tang, Leslie Yip

Department of Electrical Engineering

Research output: Journal Publications and Reviews › RGC 22 - Publication in policy or professional journal

40 Citations (Scopus)

Abstract

In this paper, a hardware implementation of genetic algorithm using field-programmable gate arrays (FPGAs) is described and implemented. Such development can greatly improve the speed of genetic algorithm by the hardware parallel and pipelined architectures. In our design, various configurations of parallelization are available with a PCI board based design, which further helps in forming a fast optimization tool for real-world applications.

Original language	English
Journal	Midwest Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/MWSCAS.2004.1354049
Publication status	Published - 2004
Event	The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan Duration: 25 Jul 2004 → 28 Jul 2004

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title = "Hardware implementation of genetic algorithms using FPGA",

abstract = "In this paper, a hardware implementation of genetic algorithm using field-programmable gate arrays (FPGAs) is described and implemented. Such development can greatly improve the speed of genetic algorithm by the hardware parallel and pipelined architectures. In our design, various configurations of parallelization are available with a PCI board based design, which further helps in forming a fast optimization tool for real-world applications.",

author = "Wallace Tang and Leslie Yip",

year = "2004",

doi = "10.1109/MWSCAS.2004.1354049",

language = "English",

volume = "1",

journal = "Midwest Symposium on Circuits and Systems",

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note = "The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings ; Conference date: 25-07-2004 Through 28-07-2004",

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AU - Tang, Wallace

AU - Yip, Leslie

PY - 2004

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AB - In this paper, a hardware implementation of genetic algorithm using field-programmable gate arrays (FPGAs) is described and implemented. Such development can greatly improve the speed of genetic algorithm by the hardware parallel and pipelined architectures. In our design, various configurations of parallelization are available with a PCI board based design, which further helps in forming a fast optimization tool for real-world applications.

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U2 - 10.1109/MWSCAS.2004.1354049

DO - 10.1109/MWSCAS.2004.1354049

M3 - RGC 22 - Publication in policy or professional journal

SN - 1548-3746

VL - 1

JO - Midwest Symposium on Circuits and Systems

JF - Midwest Symposium on Circuits and Systems

T2 - The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings

Y2 - 25 July 2004 through 28 July 2004

ER -

Hardware implementation of genetic algorithms using FPGA

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