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Graphical modelling of pinched hysteresis loops of memristors

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

Abstract

In this study, a graphical modelling approach of the pinched hysteresis loops exhibited by memristors is presented. This method provides a tool to emulate the hysteresis loop pinched at the origin, with the lobe area varying with the excitation frequency. The direction of the pinched hysteresis loop can be controlled. This graphical modelling method provides an alternative to describe the behaviour of memristors without deriving the coupled non-linear differential equations typically required for physical memristors. The method has been successfully applied to model the Hewlett-Packard memristor device. © The Institution of Engineering and Technology 2016.
Original languageEnglish
Pages (from-to)86-96
JournalIET Science, Measurement and Technology
Volume11
Issue number1
DOIs
Publication statusPublished - 1 Jan 2017
Externally publishedYes

Bibliographical note

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