Gate leakage properties of MOS devices with TriLayer high-k gate dielectric

W. B. Chen; J. P. Xu; P. T. Lai; Y. P. Li; S. G. Xu

doi:10.1109/EDSSC.2005.1635370

Gate leakage properties of MOS devices with TriLayer high-k gate dielectric

W. B. Chen
, J. P. Xu
, P. T. Lai
, Y. P. Li
, S. G. Xu

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

Abstract

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked for MOSFET's with SiO₂and high-k dielectric material as gate dielectric respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a Si/SiO₂-like interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5- nm HfO₂and 1.2-nm HfSiON exhibits the lowest gate leakage. ©2005 IEEE.

Original language	English
Title of host publication	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Publisher	IEEE
Pages	695-698
ISBN (Print)	0780393392, 9780780393394
DOIs	https://doi.org/10.1109/EDSSC.2005.1635370
Publication status	Published - 2005
Externally published	Yes
Event	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon, Hong Kong, China Duration: 19 Dec 2005 → 21 Dec 2005

Publication series

Name	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Conference

Conference	2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
Place	Hong Kong, China
City	Howloon
Period	19/12/05 → 21/12/05

Bibliographical note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

Funding

This work is financially supported by the National Natural Science Foundation of China (NSFC, Grant No. 60376019) and the Natural Science Foundation of Hubei Province of China (Grant No. 2003ABA087).

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10.1109/EDSSC.2005.1635370

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Chen, W. B., Xu, J. P., Lai, P. T., Li, Y. P., & Xu, S. G. (2005). Gate leakage properties of MOS devices with TriLayer high-k gate dielectric. In 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC (pp. 695-698). Article 1635370 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC). IEEE. https://doi.org/10.1109/EDSSC.2005.1635370

@inproceedings{d4cfe9bd90f74bc298e16e4108c66f04,

title = "Gate leakage properties of MOS devices with TriLayer high-k gate dielectric",

abstract = "Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked for MOSFET's with SiO2and high-k dielectric material as gate dielectric respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO2/HfSiON with a U-shape nitrogen profile and a Si/SiO2-like interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5- nm HfO2and 1.2-nm HfSiON exhibits the lowest gate leakage. {\textcopyright}2005 IEEE.",

author = "Chen, \{W. B.\} and Xu, \{J. P.\} and Lai, \{P. T.\} and Li, \{Y. P.\} and Xu, \{S. G.\}",

note = "Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].; 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC ; Conference date: 19-12-2005 Through 21-12-2005",

year = "2005",

doi = "10.1109/EDSSC.2005.1635370",

language = "English",

isbn = "0780393392",

series = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

publisher = "IEEE",

pages = "695--698",

booktitle = "2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC",

address = "United States",

}

Chen, WB, Xu, JP, Lai, PT, Li, YP & Xu, SG 2005, Gate leakage properties of MOS devices with TriLayer high-k gate dielectric. in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC., 1635370, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, IEEE, pp. 695-698, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC, Howloon, Hong Kong, China, 19/12/05. https://doi.org/10.1109/EDSSC.2005.1635370

Gate leakage properties of MOS devices with TriLayer high-k gate dielectric. / Chen, W. B.; Xu, J. P.; Lai, P. T. et al.
2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC. IEEE, 2005. p. 695-698 1635370 (2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - Gate leakage properties of MOS devices with TriLayer high-k gate dielectric

AU - Chen, W. B.

AU - Xu, J. P.

AU - Lai, P. T.

AU - Li, Y. P.

AU - Xu, S. G.

N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

PY - 2005

Y1 - 2005

N2 - Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked for MOSFET's with SiO2and high-k dielectric material as gate dielectric respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO2/HfSiON with a U-shape nitrogen profile and a Si/SiO2-like interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5- nm HfO2and 1.2-nm HfSiON exhibits the lowest gate leakage. ©2005 IEEE.

AB - Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked for MOSFET's with SiO2and high-k dielectric material as gate dielectric respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO2/HfSiON with a U-shape nitrogen profile and a Si/SiO2-like interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5- nm HfO2and 1.2-nm HfSiON exhibits the lowest gate leakage. ©2005 IEEE.

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U2 - 10.1109/EDSSC.2005.1635370

DO - 10.1109/EDSSC.2005.1635370

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 0780393392

SN - 9780780393394

T3 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

SP - 695

EP - 698

BT - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

PB - IEEE

T2 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Y2 - 19 December 2005 through 21 December 2005

ER -

Gate leakage properties of MOS devices with TriLayer high-k gate dielectric

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