G-AETCAM : Gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

23 Scopus Citations
View graph of relations

Author(s)

Detail(s)

Original languageEnglish
Article number8049445
Pages (from-to)20785-20790
Number of pages6
Journal / PublicationIEEE Access
Volume5
Online published26 Sep 2017
Publication statusPublished - 2017
Externally publishedYes

Abstract

This paper presents a novel architecture for ternary content-addressable memory (TCAM), using G-AETCAM cells, which outputs the address of the provided input data. The proposed architecture is a matrix of G-AETCAM cells arranged in the form of rows and columns using flip-flop as a memory element and a control logic circuitry consisting of logic gates. One G-AETCAM cell encodes the input and stored bit into one encoded bit which results in a match-line after passing from the AND-gate-array. Many architectures configure random-access memory (RAM) available on FPGAs as content-addressable storage architecture but are efficient for specific size and deal with data only in ascending or descending order while the proposed architecture provides freedom in size with no chance of making a single memory cell as useless and can store ternary data in any order. RAM-based TCAMs require pre-processing for the storage of TCAM words while the proposed design does not involve any pre-processing. The proposed architecture reduces the transistor count by a factor of 25.55, as compared with the RAM-based TCAM, which ultimately reduces area and increases the speed of operations. The proposed architecture is successfully implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 and achieves a speed of 358 MHz.

Research Area(s)

  • Content-addressable storage, field-programmable gate arrays, flip-flops, logic gates, memory, RAM-based TCAM