TY - GEN
T1 - Future Computing Platform Design
T2 - 24th Design, Automation and Test in Europe Conference, DATE 2021
AU - Cheng, Hsiang-Yun
AU - Wu, Chun-Feng
AU - Hakert, Christian
AU - Chen, Kuan-Hsun
AU - Chang, Yuan-Hao
AU - Chen, Jian-Jia
AU - Yang, Chia-Lin
AU - Kuo, Tei-Wei
PY - 2021
Y1 - 2021
N2 - Future computing platforms are facing a paradigm shift with the emerging resistive memory technologies. First, they offer fast memory accesses and data persistence in a single large-capacity device deployed on the memory bus, blurring the boundary between memory and storage. Second, they enable computing-in-memory for neuromorphic computing to mitigate costly data movements. Due to the non-ideality of these resistive memory devices at the moment, we envision that cross-layer design is essential to bring such a system into practice. In this paper, we showcase a few examples to demonstrate how cross-layer design can be developed to fully exploit the potential of resistive memories and accelerate its adoption for future computing platforms.
AB - Future computing platforms are facing a paradigm shift with the emerging resistive memory technologies. First, they offer fast memory accesses and data persistence in a single large-capacity device deployed on the memory bus, blurring the boundary between memory and storage. Second, they enable computing-in-memory for neuromorphic computing to mitigate costly data movements. Due to the non-ideality of these resistive memory devices at the moment, we envision that cross-layer design is essential to bring such a system into practice. In this paper, we showcase a few examples to demonstrate how cross-layer design can be developed to fully exploit the potential of resistive memories and accelerate its adoption for future computing platforms.
UR - https://www.scopus.com/pages/publications/85111037204
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-85111037204&origin=recordpage
U2 - 10.23919/DATE51398.2021.9474229
DO - 10.23919/DATE51398.2021.9474229
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 978-1-7281-6336-9
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 312
EP - 317
BT - Proceedings of the 2021 Design, Automation & Test in Europe (DATE 2021)
PB - IEEE
Y2 - 1 February 2021 through 5 February 2021
ER -