FPGA implementation of pairings using residue number system and lazy reduction

Ray C. C. Cheung; Sylvain Duquesne; Junfeng Fan; Nicolas Guillermin; Ingrid Verbauwhede; Gavin Xiaoxu Yao

doi:10.1007/978-3-642-23951-9_28

FPGA implementation of pairings using residue number system and lazy reduction

Ray C. C. Cheung, Sylvain Duquesne, Junfeng Fan, Nicolas Guillermin, Ingrid Verbauwhede, Gavin Xiaoxu Yao

Department of Electrical Engineering

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

66 Citations (Scopus)

Abstract

Recently, a lot of progress has been made in the implementation of pairings in both hardware and software. In this paper, we present two FPGA-based high speed pairing designs using the Residue Number System and lazy reduction. We show that by combining RNS, which is naturally suitable for parallel architectures, and lazy reduction, which performs one reduction for multiple multiplications, the speed of pairing computation in hardware can be largely increased. The results show that both designs achieve higher speed than previous designs. The fastest version computes an optimal ate pairing at 126-bit security level in 0.573 ms, which is 2 times faster than all previous hardware implementations at the same security level. © 2011 International Association for Cryptologic Research.

Original language	English
Title of host publication	Cryptographic Hardware and Embedded Systems
Subtitle of host publication	13th International Workshop, CHES 2011, Proceedings
Publisher	Springer Verlag
Pages	421-441
Volume	6917 LNCS
ISBN (Print)	9783642239502
DOIs	https://doi.org/10.1007/978-3-642-23951-9_28
Publication status	Published - 2011
Event	13th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2011 - Nara, Japan Duration: 28 Sept 2011 → 1 Oct 2011

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	6917 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	13th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2011
Place	Japan
City	Nara
Period	28/09/11 → 1/10/11

Research Keywords

FPGA
Lazy Reduction
Optimal Pairing
Residue Number System

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10.1007/978-3-642-23951-9_28

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Cheung, R. C. C., Duquesne, S., Fan, J., Guillermin, N., Verbauwhede, I., & Yao, G. X. (2011). FPGA implementation of pairings using residue number system and lazy reduction. In Cryptographic Hardware and Embedded Systems: 13th International Workshop, CHES 2011, Proceedings (Vol. 6917 LNCS, pp. 421-441). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6917 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-642-23951-9_28

Cheung, Ray C. C. ; Duquesne, Sylvain ; Fan, Junfeng et al. / FPGA implementation of pairings using residue number system and lazy reduction. Cryptographic Hardware and Embedded Systems: 13th International Workshop, CHES 2011, Proceedings. Vol. 6917 LNCS Springer Verlag, 2011. pp. 421-441 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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title = "FPGA implementation of pairings using residue number system and lazy reduction",

abstract = "Recently, a lot of progress has been made in the implementation of pairings in both hardware and software. In this paper, we present two FPGA-based high speed pairing designs using the Residue Number System and lazy reduction. We show that by combining RNS, which is naturally suitable for parallel architectures, and lazy reduction, which performs one reduction for multiple multiplications, the speed of pairing computation in hardware can be largely increased. The results show that both designs achieve higher speed than previous designs. The fastest version computes an optimal ate pairing at 126-bit security level in 0.573 ms, which is 2 times faster than all previous hardware implementations at the same security level. {\textcopyright} 2011 International Association for Cryptologic Research.",

keywords = "FPGA, Lazy Reduction, Optimal Pairing, Residue Number System",

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Cheung, RCC, Duquesne, S, Fan, J, Guillermin, N, Verbauwhede, I & Yao, GX 2011, FPGA implementation of pairings using residue number system and lazy reduction. in Cryptographic Hardware and Embedded Systems: 13th International Workshop, CHES 2011, Proceedings. vol. 6917 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 6917 LNCS, Springer Verlag, pp. 421-441, 13th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2011, Nara, Japan, 28/09/11. https://doi.org/10.1007/978-3-642-23951-9_28

FPGA implementation of pairings using residue number system and lazy reduction. / Cheung, Ray C. C.; Duquesne, Sylvain; Fan, Junfeng et al.
Cryptographic Hardware and Embedded Systems: 13th International Workshop, CHES 2011, Proceedings. Vol. 6917 LNCS Springer Verlag, 2011. p. 421-441 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 6917 LNCS).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - FPGA implementation of pairings using residue number system and lazy reduction

AU - Cheung, Ray C. C.

AU - Duquesne, Sylvain

AU - Fan, Junfeng

AU - Guillermin, Nicolas

AU - Verbauwhede, Ingrid

AU - Yao, Gavin Xiaoxu

PY - 2011

Y1 - 2011

N2 - Recently, a lot of progress has been made in the implementation of pairings in both hardware and software. In this paper, we present two FPGA-based high speed pairing designs using the Residue Number System and lazy reduction. We show that by combining RNS, which is naturally suitable for parallel architectures, and lazy reduction, which performs one reduction for multiple multiplications, the speed of pairing computation in hardware can be largely increased. The results show that both designs achieve higher speed than previous designs. The fastest version computes an optimal ate pairing at 126-bit security level in 0.573 ms, which is 2 times faster than all previous hardware implementations at the same security level. © 2011 International Association for Cryptologic Research.

AB - Recently, a lot of progress has been made in the implementation of pairings in both hardware and software. In this paper, we present two FPGA-based high speed pairing designs using the Residue Number System and lazy reduction. We show that by combining RNS, which is naturally suitable for parallel architectures, and lazy reduction, which performs one reduction for multiple multiplications, the speed of pairing computation in hardware can be largely increased. The results show that both designs achieve higher speed than previous designs. The fastest version computes an optimal ate pairing at 126-bit security level in 0.573 ms, which is 2 times faster than all previous hardware implementations at the same security level. © 2011 International Association for Cryptologic Research.

KW - FPGA

KW - Lazy Reduction

KW - Optimal Pairing

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SN - 9783642239502

VL - 6917 LNCS

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 421

EP - 441

BT - Cryptographic Hardware and Embedded Systems

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ER -

Cheung RCC, Duquesne S, Fan J, Guillermin N, Verbauwhede I, Yao GX. FPGA implementation of pairings using residue number system and lazy reduction. In Cryptographic Hardware and Embedded Systems: 13th International Workshop, CHES 2011, Proceedings. Vol. 6917 LNCS. Springer Verlag. 2011. p. 421-441. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-642-23951-9_28

FPGA implementation of pairings using residue number system and lazy reduction

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