Abstract
We present a full-parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. The proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Accumulation) component; a second stage containing a prethreshold potential updating unit with an error approximation function component; and a third stage consisting of a gradient calculation unit. A flexible and efficient architecture that can accommodate different design speed requirements is generated. The design runs on a Xilinx Virtex-6 FPGA and the processing core produces data samples at a speed of 1.33 × 106 data frames/sec, which is 3.1 × 103 times faster than the corresponding C model running on an Intel i7-860 Quad Core Processor. © 2011 IEEE.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011 |
| Pages | 44-49 |
| DOIs | |
| Publication status | Published - 2011 |
| Event | 21st International Conference on Field Programmable Logic and Applications, FPL 2011 - Chania, Greece Duration: 5 Sept 2011 → 7 Sept 2011 |
Conference
| Conference | 21st International Conference on Field Programmable Logic and Applications, FPL 2011 |
|---|---|
| Place | Greece |
| City | Chania |
| Period | 5/09/11 → 7/09/11 |
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