TY - GEN
T1 - First Demonstration of an Ultra-Wide Bandgap Power Module through Device-Package, Electro-Thermo-Mechanical Co-Optimization
AU - Gong, Hehe
AU - Yang, Xin
AU - Wang, Boyan
AU - Zhang, Zichen
AU - Yuchi, Qingrui
AU - Yang, Zineng
AU - Wang, Zhengpeng
AU - Porter, Matthew
AU - Cui, Hongchang
AU - Qin, Yuan
AU - Wang, Yibo
AU - Wang, Xiaosheng
AU - Jiang, Chaoqiang
AU - Zhang, Rong
AU - Wang, Han
AU - Dong, Dong
AU - Ye, Jiandong
AU - Lu, Guoquan
AU - Zhang, Yuhao
PY - 2025/12
Y1 - 2025/12
N2 - We demonstrate, for the first time, an ultra-wide bandgap (UWBG) power module, which integrates 6 packaged Ga2O3 dies and achieves 1000 V and 200 A switching – over 10× higher power capacity than previously reported UWBG devices. To address Ga2O3's low thermal conductivity (kT), a junction-side-cooling (JSC) package is employed, achieving low thermal resistance. However, JSC package often degrades breakdown voltage (BV) due to high electric fields at the die edges. To overcome this, we introduce two novel interface designs between device surface and the die attach in package: a post interface and a high-κ dielectric interface. The post interface preserves the device's BV by physically distancing high-field regions, while the high-κ interface further enhances BV via polarization effects. In terms of thermal performance, the high-κ design reduces thermal resistance by 50% compared to the post design, while both enable direct JSC. Mechanically, the post provides stress relief by acting as a compliant buffer, and high-κ interface reduces stress by improving coefficients of thermal expansion (CTE) match between Ga2O3 and sintered Ag. Such improvements are validated experimentally by power cycling tests. Overall, these electro-thermo-mechanical cooptimizations offer critical guidance for module development in UWBG devices and enable a key milestone in power scaling for UWBG power technologies toward industrial applications. © 2025 IEEE.
AB - We demonstrate, for the first time, an ultra-wide bandgap (UWBG) power module, which integrates 6 packaged Ga2O3 dies and achieves 1000 V and 200 A switching – over 10× higher power capacity than previously reported UWBG devices. To address Ga2O3's low thermal conductivity (kT), a junction-side-cooling (JSC) package is employed, achieving low thermal resistance. However, JSC package often degrades breakdown voltage (BV) due to high electric fields at the die edges. To overcome this, we introduce two novel interface designs between device surface and the die attach in package: a post interface and a high-κ dielectric interface. The post interface preserves the device's BV by physically distancing high-field regions, while the high-κ interface further enhances BV via polarization effects. In terms of thermal performance, the high-κ design reduces thermal resistance by 50% compared to the post design, while both enable direct JSC. Mechanically, the post provides stress relief by acting as a compliant buffer, and high-κ interface reduces stress by improving coefficients of thermal expansion (CTE) match between Ga2O3 and sintered Ag. Such improvements are validated experimentally by power cycling tests. Overall, these electro-thermo-mechanical cooptimizations offer critical guidance for module development in UWBG devices and enable a key milestone in power scaling for UWBG power technologies toward industrial applications. © 2025 IEEE.
UR - https://www.scopus.com/pages/publications/105033575387
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-105033575387&origin=recordpage
U2 - 10.1109/IEDM50572.2025.11353633
DO - 10.1109/IEDM50572.2025.11353633
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 979-8-3315-6786-6
T3 - Technical Digest - International Electron Devices Meeting, IEDM
BT - 2025 IEEE International Electron Devices Meeting (IEDM)
PB - IEEE
T2 - 2025 IEEE International Electron Devices Meeting (IEDM 2025)
Y2 - 6 December 2025 through 10 December 2025
ER -