Fast, area-efficient CMOS parity generation

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review

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Author(s)

Detail(s)

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages874-876
Volume2
ISBN (Print)780300815
Publication statusPublished - 1991
Externally publishedYes

Publication series

Name
Volume2

Conference

Title33rd Midwest Symposium on Circuits and Systems
CityCalgary, Alberta, Can
Period12 - 15 August 1990

Abstract

High-performance CMOS parity generator cells are described. Their enhanced speed is derived principally from a combination of exclusive-or and equivalence gate circuits. The circuits realize these logic functions in a single gate level using a combination of fully restoring and pass-transistor gate topology in a semirestoring configuration. The circuits are suitable for the gate forest realization. These parity generator cells neither consume DC power nor require complementary input signals, and are approximately three to five times faster than the conventional dual-level logic implementation. When these circuits are cascaded, the noise margin degradation problems typically associated with nonrestoring logic families are improved. The simplicity of this approach provides significant area savings compared to conventional implementations of various types.

Citation Format(s)

Fast, area-efficient CMOS parity generation. / Wu, Angus; Meador, Jack.

Midwest Symposium on Circuits and Systems. Vol. 2 Publ by IEEE, 1991. p. 874-876.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review