Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

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Detail(s)

Original languageEnglish
Pages (from-to)475-488
Number of pages14
Journal / PublicationIEEE Transactions on Computers
Volume69
Issue number4
Online published18 Dec 2019
Publication statusPublished - Apr 2020

Abstract

By stacking layers vertically, the adoption of 3D NAND has significantly increased the capacity for storage systems. The complex structure of 3D NAND introduces more errors than planer flash. To address the reliability issue, low-density parity-check (LDPC) code with a strong error correction capability is now widely applied on 3D NAND flash memory. However, LDPC has long decoding latency when the raw bit error rates (RBER) are high. This is because it needs fine-grained soft sensing between voltage states to iteratively decode the raw data. Multiple sensing voltages are applied on flash cell array to gain necessary information for decoding. In this article, a new sensing level placement scheme with reduced number of sensing levels is proposed. The basic idea for the placement scheme is motivated by three asymmetric error characteristics of flash memory: the asymmetric errors between different states, the asymmetric errors caused by voltage left-shifts and right-shifts and asymmetric errors among layers in a 3D NAND flash block. With awareness of these three types of error characteristics, reduced number of sensing levels are placed to achieve reduced read latency for LDPC decoding while maintaining the error correction capability of LDPC. Experiment analysis shows that the proposed scheme achieves significant performance improvement.

Research Area(s)

  • Asymmetric errors, LDPC, sensing level placement, NAND flash memory