TY - JOUR
T1 - Error model guided joint performance and endurance optimization for flash memory
AU - Shi, Liang
AU - Qiu, Keni
AU - Zhao, Mengying
AU - Xue, Chun Jason
PY - 2014/3
Y1 - 2014/3
N2 - As flash memory has better performance than hard disks, it has been widely applied in embedded systems, personal computers, and data centers as storage components. However, endurance and write performance are the two key challenges in the deployment of flash memory. In this paper, with the awareness of errors induced from write operations, endurance, and retention time, a stage-based optimization approach is proposed to improve the write performance and endurance at different usage stages of flash memory. A series of trace-driven simulations show that the proposed approach outperforms a set of state-of-the-art approaches in terms of write performance and lifetime.
AB - As flash memory has better performance than hard disks, it has been widely applied in embedded systems, personal computers, and data centers as storage components. However, endurance and write performance are the two key challenges in the deployment of flash memory. In this paper, with the awareness of errors induced from write operations, endurance, and retention time, a stage-based optimization approach is proposed to improve the write performance and endurance at different usage stages of flash memory. A series of trace-driven simulations show that the proposed approach outperforms a set of state-of-the-art approaches in terms of write performance and lifetime.
KW - Endurance error
KW - error model
KW - retention error
KW - smart refresh
KW - stage optimization
KW - write error
UR - http://www.scopus.com/inward/record.url?scp=84897598008&partnerID=8YFLogxK
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84897598008&origin=recordpage
U2 - 10.1109/TCAD.2013.2288691
DO - 10.1109/TCAD.2013.2288691
M3 - RGC 21 - Publication in refereed journal
SN - 0278-0070
VL - 33
SP - 343
EP - 355
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 3
M1 - 6740049
ER -