Energy-efficient joint scheduling and application-specific interconnection design

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Original languageEnglish
Article number5565543
Pages (from-to)1813-1822
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
Publication statusPublished - Oct 2011


Energy-efficient and high-performance interconnections are critical for multiprocessor architectures. As technology moves into deep submicrometer level, static and dynamic energy consumptions have become dominant constraint factors in high-performance system design. This paper jointly considers scheduling and interconnection design to minimize the interconnection's energy consumption without performance degradation. The Interconnection Energy Minimization Scheduling algorithm is proposed in this paper to design interconnection with segmented buses and to determine a feasible computation and communication schedule to minimize interconnection's energy consumption while meeting tight-latency and high-volume data transfer needs for applications with large inherited parallelism. Experimental results show that interconnection's dynamic energy consumption can be reduced by about 71% and static energy consumption can be reduced by about 35% on average when the proposed algorithm is compared with existing communication cost-conscious scheduling techniques for the evaluated digital signal processing and media applications. © 2010 IEEE.

Research Area(s)

  • high-level synthesis, Interconnection network, low power, multiprocessor architecture, network on chip