Energy-efficient H.264 video decoding on VLIW embedded processors

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)22_Publication in policy or professional journal

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Author(s)

Detail(s)

Original languageEnglish
Article number2
Pages (from-to)9-20
Journal / PublicationProceedings of SPIE - The International Society for Optical Engineering
Volume5683
Publication statusPublished - 2005
Externally publishedYes

Conference

TitleProceedings of SPIE-IS and T Electronic Imaging - Embedded Processors for Multimedia and Communications II
PlaceUnited States
CitySan Jose, CA
Period17 - 18 January 2005

Abstract

The energy consumption profiling of the H.264 video decoder on VLIW embedded processors using the Trimaran simulator is conducted. Based on this study, we observe that the branch operations in the quarter-pixel (QP) interpolation and the DCT slow down the issue rate of the VLIW processors. Then, several new instruction architecture sets are proposed to address this issue. These new instructions can be used to speedup the issue rate, and reduce the total energy consumption. Finally, experimental results of the proposed instruction-level power-efficient strategies on the TI C6416 processor are reported and discussed. © 2005 SPIE and IS&T.

Research Area(s)

  • Embedded processor, Energy optimization, H.264, VLIW