Efficient VLSI implementation of four-step search algorithm

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Detail(s)

Original languageEnglish
Pages (from-to)503-506
Journal / PublicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume3
Publication statusPublished - 1998

Conference

Title1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98)
LocationInstituto Superior Técnico
PlacePortugal
CityLisboa
Period7 - 10 September 1998

Abstract

Four-step search (4SS) performs better than well known three-step search (3SS) and new three-step search (N3SS). Since 3SS, N3SS and 4SS are similar algorithms, existing architectures for 3SS and N3SS can be used for 4SS implementation. However, direct implementation of 4SS by existing architectures will cause redundant search. A power efficient VLSI implementation for 4SS is proposed. The implementation will focus on power reduction through power down technique by dedicated data flow control and usage of calculation elements. The simulation result shows the proposed method increases the system throughput and reduces power consumption by 40%.