Efficient VLSI implementation of four-step search algorithm
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Pages (from-to) | 503-506 |
| Journal / Publication | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| Volume | 3 |
| Publication status | Published - 1998 |
Conference
| Title | 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) |
|---|---|
| Location | Instituto Superior Técnico |
| Place | Portugal |
| City | Lisboa |
| Period | 7 - 10 September 1998 |
Link(s)
Abstract
Four-step search (4SS) performs better than well known three-step search (3SS) and new three-step search (N3SS). Since 3SS, N3SS and 4SS are similar algorithms, existing architectures for 3SS and N3SS can be used for 4SS implementation. However, direct implementation of 4SS by existing architectures will cause redundant search. A power efficient VLSI implementation for 4SS is proposed. The implementation will focus on power reduction through power down technique by dedicated data flow control and usage of calculation elements. The simulation result shows the proposed method increases the system throughput and reduces power consumption by 40%.
Citation Format(s)
Efficient VLSI implementation of four-step search algorithm. / Wu, Angus; So, Man F.
In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 3, 1998, p. 503-506.Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
