Efficient VLSI implementation of four-step search algorithm

Angus Wu; Man F. So

doi:10.1109/ICECS.1998.814058

Efficient VLSI implementation of four-step search algorithm

Angus Wu
, Man F. So

City University of Hong Kong

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

1 Citation (Scopus)

Abstract

Four-step search (4SS) performs better than well known three-step search (3SS) and new three-step search (N3SS). Since 3SS, N3SS and 4SS are similar algorithms, existing architectures for 3SS and N3SS can be used for 4SS implementation. However, direct implementation of 4SS by existing architectures will cause redundant search. A power efficient VLSI implementation for 4SS is proposed. The implementation will focus on power reduction through power down technique by dedicated data flow control and usage of calculation elements. The simulation result shows the proposed method increases the system throughput and reduces power consumption by 40%.

Original language	English
Pages (from-to)	503-506
Journal	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	3
DOIs	https://doi.org/10.1109/ICECS.1998.814058
Publication status	Published - 1998
Event	1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98): Surfing the Waves of Science and Technology - Instituto Superior Técnico, Lisboa, Portugal Duration: 7 Sept 1998 → 10 Sept 1998

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title = "Efficient VLSI implementation of four-step search algorithm",

abstract = "Four-step search (4SS) performs better than well known three-step search (3SS) and new three-step search (N3SS). Since 3SS, N3SS and 4SS are similar algorithms, existing architectures for 3SS and N3SS can be used for 4SS implementation. However, direct implementation of 4SS by existing architectures will cause redundant search. A power efficient VLSI implementation for 4SS is proposed. The implementation will focus on power reduction through power down technique by dedicated data flow control and usage of calculation elements. The simulation result shows the proposed method increases the system throughput and reduces power consumption by 40\%.",

author = "Angus Wu and So, \{Man F.\}",

year = "1998",

doi = "10.1109/ICECS.1998.814058",

language = "English",

volume = "3",

pages = "503--506",

journal = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

note = "1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) : Surfing the Waves of Science and Technology ; Conference date: 07-09-1998 Through 10-09-1998",

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TY - JOUR

T1 - Efficient VLSI implementation of four-step search algorithm

AU - Wu, Angus

AU - So, Man F.

PY - 1998

Y1 - 1998

N2 - Four-step search (4SS) performs better than well known three-step search (3SS) and new three-step search (N3SS). Since 3SS, N3SS and 4SS are similar algorithms, existing architectures for 3SS and N3SS can be used for 4SS implementation. However, direct implementation of 4SS by existing architectures will cause redundant search. A power efficient VLSI implementation for 4SS is proposed. The implementation will focus on power reduction through power down technique by dedicated data flow control and usage of calculation elements. The simulation result shows the proposed method increases the system throughput and reduces power consumption by 40%.

AB - Four-step search (4SS) performs better than well known three-step search (3SS) and new three-step search (N3SS). Since 3SS, N3SS and 4SS are similar algorithms, existing architectures for 3SS and N3SS can be used for 4SS implementation. However, direct implementation of 4SS by existing architectures will cause redundant search. A power efficient VLSI implementation for 4SS is proposed. The implementation will focus on power reduction through power down technique by dedicated data flow control and usage of calculation elements. The simulation result shows the proposed method increases the system throughput and reduces power consumption by 40%.

UR - https://www.scopus.com/pages/publications/0032264309

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-0032264309&origin=recordpage

U2 - 10.1109/ICECS.1998.814058

DO - 10.1109/ICECS.1998.814058

M3 - RGC 21 - Publication in refereed journal

VL - 3

SP - 503

EP - 506

JO - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

JF - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

T2 - 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98)

Y2 - 7 September 1998 through 10 September 1998

ER -

Efficient VLSI implementation of four-step search algorithm

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