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Efficient implementation technique of LDPC decoder

W. K. Leung, W. L. Lee, A. Wu, L. Ping

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

Abstract

An efficient implementation technique of the low density parity check (LDPC) code decoder based on the parity-likelihood-ratio (PLR) was analyzed. The technique does not require multiplication or table searching and allows the decoder to be implemented with additions only. It involves lower complexity and is less sensitive to the quantization effect as compared to the standard sum-product decoder. The performance of the five-bit scheme with the correction term was found to be close to that of the ideal case.
Original languageEnglish
Pages (from-to)1231-1232
JournalElectronics Letters
Volume37
Issue number20
DOIs
Publication statusPublished - 27 Sept 2001

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