Efficient implementation technique of LDPC decoder
Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Pages (from-to) | 1231-1232 |
| Journal / Publication | Electronics Letters |
| Volume | 37 |
| Issue number | 20 |
| Publication status | Published - 27 Sep 2001 |
Link(s)
Abstract
An efficient implementation technique of the low density parity check (LDPC) code decoder based on the parity-likelihood-ratio (PLR) was analyzed. The technique does not require multiplication or table searching and allows the decoder to be implemented with additions only. It involves lower complexity and is less sensitive to the quantization effect as compared to the standard sum-product decoder. The performance of the five-bit scheme with the correction term was found to be close to that of the ideal case.
Citation Format(s)
Efficient implementation technique of LDPC decoder. / Leung, W. K.; Lee, W. L.; Wu, A. et al.
In: Electronics Letters, Vol. 37, No. 20, 27.09.2001, p. 1231-1232.Research output: Journal Publications and Reviews (RGC: 21, 22, 62) › 21_Publication in refereed journal › peer-review
