Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

15 Scopus Citations
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Author(s)

  • Xianzhang Chen
  • Edwin Hsing-Mean Sha
  • Qingfeng Zhuge
  • Weiwen Jiang
  • Yuangang Wang

Related Research Unit(s)

Detail(s)

Original languageEnglish
Article number7445241
Pages (from-to)3094-3104
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number10
Publication statusPublished - 1 Oct 2016

Abstract

A domain-wall memory (DWM) is becoming an attractive candidate to replace the traditional memories for its high density, low-power leakage, and low access latency. Accessing data on DWM is accomplished by shift operations that move data located on nanowires to read/write ports. Due to this kind of construction, data accesses on DWM exhibit varying access latencies. Therefore, data placement (DP) strategy has a significant impact on the performance of data accesses on DWM. In this paper, we prove the nondeterministic polynomial time (NP)-completeness of the DP problem on DWM. For the DWMs organized in single DWM block cluster (DBC), we present integer linear programming formulations to solve the problem optimally. We also propose an efficient single DBC placement (S-DBC-P) algorithm to exploit the benefits of multiple read/write ports and data locality. Compared with the sequential DP strategy, S-DBC-P reduces 76.9% shift operations on average for eight-port DWMs. Furthermore, for DP problem on the DWMs organized in multiple DBCs, we develop an efficient multiple DBC placement (M-DBC-P) algorithm to utilize the parallelism of DBCs. The experimental results show that the M-DBC-P achieves 90% performance improvement over the sequential DP strategy.

Research Area(s)

  • Data placement (DP), domain-wall memory (DWM), optimization, shift operation

Citation Format(s)

Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory. / Chen, Xianzhang; Sha, Edwin Hsing-Mean; Zhuge, Qingfeng; Xue, Chun Jason; Jiang, Weiwen; Wang, Yuangang.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 10, 7445241, 01.10.2016, p. 3094-3104.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review