E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of 512×36 of E-TCAM has been successfully implemented on Xilinx Virtex-5, Virtex-6, and Virtex-7 field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains 33.33 % reduction in block-RAMs, 71.07 % in slice registers, 77.16 % in lookup tables, 53.54 % in energy/bit/search, and offers 63.03 % improvement in speed, compared with the best available SRAM-based TCAM designs.