DYNAMIC RECONFIGURATION FOR FAULT-TOLERANT SYSTOLIC ARRAYS.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review

View graph of relations

Author(s)

Detail(s)

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherPennsylvania State Univ Press
Pages110-113
ISBN (Print)271006080
Publication statusPublished - 1987
Externally publishedYes

Publication series

Name
ISSN (Electronic)0190-3918

Conference

TitleProc Int Conf Parallel Process 1987
CityUniversal Park, PA, USA
Period17 - 21 August 1987

Abstract

A distributed reconfiguration algorithm to restructure 2-D systolic array with faulty cells is described. The reconfiguration is based only on local information and can be done automatically. Transient faults can be covered. It is shown that a 2n multiplied by 2n array is exactly 3n-fault-tolerant when reconfigured into an n multiplied by n array. O(n**3) redundancy in the number of processing cells is sufficient to ensure successful reconfiguration into an n multiplied by n array. A systolic collector is developed to output the data at fixed ports and times.

Citation Format(s)

DYNAMIC RECONFIGURATION FOR FAULT-TOLERANT SYSTOLIC ARRAYS. / Li, H. F.; Pao, D.; Jayakumar, R.

Proceedings of the International Conference on Parallel Processing. Pennsylvania State Univ Press, 1987. p. 110-113.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)peer-review