Dual-Mode On-Chip Patch Antenna with High-Efficiency On-Antenna Power Combining

In this article, a dual-mode on-chip patch antenna with on-antenna power combining implemented in 130-nm SiGe BiCMOS technology is proposed for terahertz communications. Area-efficient characteristic is obtained by the proposed power combining method compared to the conventional combiner-based or spatial power combining approach. To illustrate the working principle, the radiation efficiency of the patch antenna is analyzed and calculated based on the quality factor of the cavity model. As such, three approaches are introduced for radiation efficiency improvement of the ultralow-profile on-chip patch antenna, i.e., properly selecting the ground plane layer, enlarging the width-to-length ratio, and introducing the mirrored patches. Then, by using the characteristic mode analysis (CMA), antiphase TM20 mode and TM12 mode are introduced for impedance bandwidth enhancement. Besides, via arrays are introduced beneath the radiator to reshape the nonbroadside pattern of TM12 mode to the broadside beam. Then, a sketch is introduced to make a design guideline. Moreover, the proposed antenna is compared with three reference antennas with other bandwidth enhancement techniques to show its superiority. Finally, the proposed antenna is fabricated and measured, demonstrating advantageous performances of wide impedance bandwidth (284–322 GHz), 3-dB gain bandwidth (285–310 GHz), and high gain (5.3 dBi) without the usage of any off-chip director. © 1963-2012 IEEE.