D-TCAM : A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

1 Scopus Citations
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Original languageEnglish
Pages (from-to)96060-96069
Journal / PublicationIEEE Access
Volume7
Online published5 Jul 2019
Publication statusPublished - 2019

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Abstract

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512times 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

Research Area(s)

  • Content-addressable memory (CAM), field-programmable gate array (FPGA), lookup table (LUT), memory, random-access memory (RAM)

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