Disturbance Relaxation for 3D Flash Memory

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

5 Scopus Citations
View graph of relations

Author(s)

  • Yu-Ming Chang
  • Yuan-Hao Chang
  • Tei-Wei Kuo
  • Yung-Chun Li
  • Hsiang-Pang Li

Detail(s)

Original languageEnglish
Article number7145418
Pages (from-to)1467-1483
Journal / PublicationIEEE Transactions on Computers
Volume65
Issue number5
Online published30 Jun 2015
Publication statusPublished - May 2016
Externally publishedYes

Abstract

Even though 3D flash memory presents a grand opportunity to huge-capacity non-volatile memory, it suffers from serious program disturbance problems. In contrast to the past efforts in error correction codes and the work in trading the space utilization for reliability, we propose a disturbance-relaxation scheme that can alleviate the negative effects caused by program disturbance inside a physical block. This scheme does not introduce any extra overheads on encoding or storing of extra redundant data. In particular, a methodology is proposed to reduce the data error rate by distributing unavoidable disturbance errors to the flash-memory space of invalid data, with the considerations of the physical organization of 3D flash memory. A series of experiments was conducted based on real multi-layer 3D flash chips, and it showed that the proposed scheme could significantly enhance the reliability of 3D flash memory.

Research Area(s)

  • 3D flash memory, disturbance, reliability

Citation Format(s)

Disturbance Relaxation for 3D Flash Memory. / Chang, Yu-Ming; Chang, Yuan-Hao; Kuo, Tei-Wei; Li, Yung-Chun; Li, Hsiang-Pang.

In: IEEE Transactions on Computers, Vol. 65, No. 5, 7145418, 05.2016, p. 1467-1483.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal