Digital hardware realization of a recurrent neural network for solving the assignment problem

The digital hardware realization of a recurrent neural network for solving the assignment problem is presented. The design is based on an analog neural network and is mapped to a one-dimensional systolic array for parallel processing. The processing elements are connected with a ring topology that reduces the overhead in controlling the pipeline. The design was simplified by exploiting regularities in the data to eliminate the need for multipliers and dividers in hardware implementation. The results of implementation and verification based on field programmable gate array device show the feasibility of the digital neural network approach to the assignment problem. © 2002 Elsevier Science B.V. All rights reserved.