Digital controlled analog architecture for DCT and DST using capacitor switching

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

9 Scopus Citations
View graph of relations



Original languageEnglish
Journal / PublicationProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2004
Externally publishedYes


Title2004 IEEE International Symposium on Cirquits and Systems - Proceedings
CityVancouver, BC
Period23 - 26 May 2004


This paper describes a sampled analog architecture, for computing DCT or DST, using switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched properly with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/ subtraction. . Proposed architecture simple, regular with lower gate count may be used for online computations.

Bibliographic Note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to