Digital controlled analog architecture for DCT and DST using capacitor switching

Arindam Basu; Ashis Kumar Mal; Anindya Sundar Dhar

doi:10.1109/iscas.2004.1329270

Digital controlled analog architecture for DCT and DST using capacitor switching

Arindam Basu
, Ashis Kumar Mal
, Anindya Sundar Dhar

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

9 Citations (Scopus)

Abstract

This paper describes a sampled analog architecture, for computing DCT or DST, using switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched properly with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/ subtraction. . Proposed architecture simple, regular with lower gate count may be used for online computations.

Original language	English
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/iscas.2004.1329270
Publication status	Published - 2004
Externally published	Yes
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004

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Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

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title = "Digital controlled analog architecture for DCT and DST using capacitor switching",

abstract = "This paper describes a sampled analog architecture, for computing DCT or DST, using switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched properly with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/ subtraction. . Proposed architecture simple, regular with lower gate count may be used for online computations.",

author = "Arindam Basu and Mal, \{Ashis Kumar\} and Dhar, \{Anindya Sundar\}",

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T1 - Digital controlled analog architecture for DCT and DST using capacitor switching

AU - Basu, Arindam

AU - Mal, Ashis Kumar

AU - Dhar, Anindya Sundar

N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

PY - 2004

Y1 - 2004

N2 - This paper describes a sampled analog architecture, for computing DCT or DST, using switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched properly with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/ subtraction. . Proposed architecture simple, regular with lower gate count may be used for online computations.

AB - This paper describes a sampled analog architecture, for computing DCT or DST, using switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched properly with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/ subtraction. . Proposed architecture simple, regular with lower gate count may be used for online computations.

UR - https://www.scopus.com/pages/publications/4344646550

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-4344646550&origin=recordpage

U2 - 10.1109/iscas.2004.1329270

DO - 10.1109/iscas.2004.1329270

M3 - RGC 21 - Publication in refereed journal

SN - 0271-4310

VL - 2

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

Digital controlled analog architecture for DCT and DST using capacitor switching

Abstract

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