Development of a new robot controller architecture with FPGA-based IC design for improved high-speed performance

In this paper, a new robot controller architecture is proposed to implement various complex control algorithms for improved high-speed performance. The main thrust of the research is to remove the servo control loop from the digital signal processor (DSP) and implement the high-speed servo loop in a field programmable gate array (FPGA). The main objective of this architecture is to utilize the ultra-high-speed hardwired logic of the FPGA to enhance the overall computational capability and relieve the computational load of the DSP for other tasks. The control algorithm is partitioned into a linear portion and a nonlinear portion. The linear portion with position/velocity feedback represents the major control loop and is implemented in the FPGA. The nonlinear portion acts as dynamic compensation to the linear portion to calculate model-related control gains/parameters, and it is implemented in the DSP. In tandem, with the newly developed control hardware architecture, an FPGA-based motion control integrated circuit (IC) is designed. Experiments are conducted on an industrial robot manipulator to compare the closed-loop performance with this new control architecture and the traditional one, when the same control algorithm is used. The experimental results demonstrate that the proposed new control architecture exhibits much improved motion performance indeed, especially in high-speed motions. © 2007 IEEE.