TY - GEN
T1 - Design Exploration for Multiple Level Cell based Non-volatile FPGAs
AU - Liu, Ke
AU - Zhao, Mengying
AU - Ju, Lei
AU - Jia, Zhiping
AU - Xue, Chun Jason
AU - Hu, Jingtong
PY - 2017/11
Y1 - 2017/11
N2 - Static random access memory (SRAM) based field programmable gate arrays (FPGAs) are currently facing challenges of limited capacity and high leakage power. To solve this problem, non-volatile memory (NVM) is proposed as the alternative to build non-volatile FPGAs (NVFPGAs). Even though the feasibility of NVFPGA has been confirmed, the utilization of multiple level cells (MLC) has not been fully exploited yet. In this paper, we study architecture of MLC based NVFPGAs, and propose five cluster structures, as well as the corresponding working mode supported by MLC based clusters. To give detailed comparisons and extensive discussions, we conduct experiments for area, performance and leakage power evaluation. Experiments show that, compared to SRAM based FPGAs, the proposed architecture can reduce the area, latency and leakage power by 32.66% and 7.45%, and 96.13%, respectively.
AB - Static random access memory (SRAM) based field programmable gate arrays (FPGAs) are currently facing challenges of limited capacity and high leakage power. To solve this problem, non-volatile memory (NVM) is proposed as the alternative to build non-volatile FPGAs (NVFPGAs). Even though the feasibility of NVFPGA has been confirmed, the utilization of multiple level cells (MLC) has not been fully exploited yet. In this paper, we study architecture of MLC based NVFPGAs, and propose five cluster structures, as well as the corresponding working mode supported by MLC based clusters. To give detailed comparisons and extensive discussions, we conduct experiments for area, performance and leakage power evaluation. Experiments show that, compared to SRAM based FPGAs, the proposed architecture can reduce the area, latency and leakage power by 32.66% and 7.45%, and 96.13%, respectively.
KW - Configurable Logic Block
KW - Multiple Level Cell
KW - Non-volatile FPGA
UR - https://www.scopus.com/pages/publications/85041637167
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-85041637167&origin=recordpage
U2 - 10.1109/ICCD.2017.46
DO - 10.1109/ICCD.2017.46
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781538622551
SP - 257
EP - 264
BT - PROCEEDINGS - IEEE 35th International Conference on Computer Design, ICCD 2017
PB - IEEE
T2 - 35th IEEE International Conference on Computer Design (ICCD 2017)
Y2 - 5 November 2017 through 8 November 2017
ER -