TY - GEN
T1 - Design automation for reconfigurable interconnection networks
AU - Fan, Hongbing
AU - Wu, Yu-Liang
AU - Cheung, Chak-Chung
PY - 2010
Y1 - 2010
N2 - A Reconfigurable Interconnection Network (RIN) is a custom designed on-chip switching network yielding routing solutions for a pre-given set of applications. Like FPGA routing networks, the RIN is used to make reconfigurable interconnections among functional blocks. Unlike FPGAs, the network topology of a RIN is irregular as it is designed for a given set of routing requirements and optimized for area, power and delay minimizations. In this paper, we propose an automatic design scheme for RINs, including routing specification formulation, graph modelings, network topology designs, routing algorithms, and MUX-based network circuit implementation. A CAD tool is developed based on the design scheme, which takes a set of routing requirements as input and produces the corresponding RIN network topology and network circuit in HDL format. We present the area costs of various RINs generated by the CAD tool with Altera's Quartus II, and illustrate the RIN design scheme with a reconfigurable multi-stream video system prototype. © 2010 Springer-Verlag.
AB - A Reconfigurable Interconnection Network (RIN) is a custom designed on-chip switching network yielding routing solutions for a pre-given set of applications. Like FPGA routing networks, the RIN is used to make reconfigurable interconnections among functional blocks. Unlike FPGAs, the network topology of a RIN is irregular as it is designed for a given set of routing requirements and optimized for area, power and delay minimizations. In this paper, we propose an automatic design scheme for RINs, including routing specification formulation, graph modelings, network topology designs, routing algorithms, and MUX-based network circuit implementation. A CAD tool is developed based on the design scheme, which takes a set of routing requirements as input and produces the corresponding RIN network topology and network circuit in HDL format. We present the area costs of various RINs generated by the CAD tool with Altera's Quartus II, and illustrate the RIN design scheme with a reconfigurable multi-stream video system prototype. © 2010 Springer-Verlag.
UR - https://www.scopus.com/pages/publications/77951285022
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-77951285022&origin=recordpage
U2 - 10.1007/978-3-642-12133-3_23
DO - 10.1007/978-3-642-12133-3_23
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 3642121322
SN - 9783642121326
VL - 5992 LNCS
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 244
EP - 256
BT - Reconfigurable Computing: Architectures, Tools and Applications
PB - Springer Verlag
T2 - 6th International Symposium on Applied Reconfigurable Computing, ARC 2010
Y2 - 17 March 2010 through 19 March 2010
ER -