Design automation algorithms for regenerative pass-transistor logic

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)22_Publication in policy or professional journal

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Original languageEnglish
Pages (from-to)1540-1543
Journal / PublicationProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 1997
Externally publishedYes


Title1997 IEEE International Symposium on Circuits and Systems (ISCAS '97)
CityHong Kong
Period9 - 12 June 1997


nMOS pass-transistor logic is one of the most popular logic families for its exclusive usage of nMOS-FETs and simple form of 2-input multiplexer and exclusive-OR gate. The nMOS-only structure is also found speedy and simple for basic logic gates. In addition, Regenerative Pass-transistor Logic (RPL) is a dual-rail pass-transistor logic with various advantages including compact layout area and high operating speed. However, in combinational logic, there are many control logics with complex structures which are difficult to be implemented in conventional pass-transistor logics. In this paper, the general design procedure and the design automation algorithms for RPL circuits under speed-power performance consideration are studied.