Design and Performance Evaluation of an FPGA based EOG Signal Preprocessor
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
Original language | English |
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Title of host publication | 3rd International Conference on Electrical, Computer and Communication Engineering |
Subtitle of host publication | ECCE 2023 |
Publisher | Institute of Electrical and Electronics Engineers, Inc. |
Number of pages | 6 |
ISBN (electronic) | 9798350345360 |
ISBN (print) | 979-8-3503-4537-7 |
Publication status | Published - 2023 |
Publication series
Name | International Conference on Electrical, Computer and Communication Engineering, ECCE |
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Conference
Title | 3rd International Conference on Electrical, Computer & Communication Engineering (ECCE 2023) |
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Place | Bangladesh |
City | Chittagong |
Period | 23 - 25 February 2023 |
Link(s)
Abstract
Electrooculogram (EOG) is an electrophysiological signal produced around the eyes due to eyeball motion. This signal can be utilized to study eye movements which is bene-ficial in many medical and bio-electrical applications such as controlling human-computer interfaces and diagnosing different ocular diseases. However, the EOG is often contaminated with high-frequency motion artifacts, 50/60 Hz grid interference, and baseline wander. Hence, the collected signals are required to be preprocessed before finally being used in applications. This paper proposes an efficient FPGA-based EOG processor for fast and real-time processing of EOG signals, especially for medical diagnosis. To the best of our knowledge, this is the first work to implement EOG serial preprocessing by FIR and IIR filters on FPGA. MATLAB's FDA tool is used for mathematical validation and primary simulation. The proposed system was implemented on the Xilinx Zynq-7000 FPGA by hardware/software co-design. By statistical analysis, the software and hardware results were found to have the Pearson Correlation Coefficient of 0.99 and a Mean Root Squared Error in the 10-3 range. The resource utilization and power consumption are presented. The on-chip power consumption for this design is 0.271 watts where dynamic power is 0.163 watts (60%), and static power is 0.108 watts (40%). Performance evaluation and comparative study of the software-hardware results revealed the efficacy of the designed EOG preprocessor. © 2023 IEEE.
Research Area(s)
- Electrooculogram, FDATool, FIR Filter, FPGA, IIR Filter, Xilinx System Gen-erator
Citation Format(s)
Design and Performance Evaluation of an FPGA based EOG Signal Preprocessor. / Das, Diba; Chowdhury, Aditta; Sanka, Abdurrashid Ibrahim et al.
3rd International Conference on Electrical, Computer and Communication Engineering: ECCE 2023. Institute of Electrical and Electronics Engineers, Inc., 2023. (International Conference on Electrical, Computer and Communication Engineering, ECCE).
3rd International Conference on Electrical, Computer and Communication Engineering: ECCE 2023. Institute of Electrical and Electronics Engineers, Inc., 2023. (International Conference on Electrical, Computer and Communication Engineering, ECCE).
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review