Design and investigation of stability- and power-improved 11T SRAM cell for low-power devices

The modern system-on-chips require stable and low-power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability- and power-improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross-coupled structure of a conventional inverter with a N-type stacked transistor and a Schmitt-trigger (ST) with a double channel-length pull-up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback-cutting N-type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (T_RA)/write delay (T_WA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel-length of pull-up transistor in the ST inverter. The moderate read/write frequency and single-ended structure of the suggested cell result in low dynamic power. Simulated results by using 16-nm CMOS at V_DD = 0.7 V show that the proposed cell has the second-best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write-half-select-disturbance issues to support bit-interleaving architecture to increase soft error immunity.