DELTRON: Neuromorphic architectures for delay based learning

Shaista Hussain; Arindam Basu; Mark Wang; Tara Julia Hamilton

doi:10.1109/APCCAS.2012.6419032

DELTRON: Neuromorphic architectures for delay based learning

Shaista Hussain
, Arindam Basu
, Mark Wang
, Tara Julia Hamilton

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

14 Citations (Scopus)

Abstract

We present a neuromorphic spiking neural network, the DELTRON, that can remember and store patterns by changing the delays of every connection as opposed to modifying the weights. The advantage of this architecture over traditional weight based ones is simpler hardware implementation without multipliers or digital-analog converters (DACs). The name is derived due to similarity in the learning rule with an earlier architecture called Tempotron. We present simulations of memory capacity of the DELTRON for different random spatio-temporal spike patterns and also present SPICE simulation results of the core circuits involved in a reconfigurable mixed signal implementation of this architecture. © 2012 IEEE.

Original language	English
Title of host publication	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Pages	304-307
DOIs	https://doi.org/10.1109/APCCAS.2012.6419032
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan, China Duration: 2 Dec 2012 → 5 Dec 2012

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Place	Taiwan, China
City	Kaohsiung
Period	2/12/12 → 5/12/12

Bibliographical note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

Access Output

10.1109/APCCAS.2012.6419032

Other Access Options

Check CityUHK Library

Permanent Link

Right click to copy link

Cite this

@inproceedings{57368553e4164a6fa2369a9a669b4409,

title = "DELTRON: Neuromorphic architectures for delay based learning",

abstract = "We present a neuromorphic spiking neural network, the DELTRON, that can remember and store patterns by changing the delays of every connection as opposed to modifying the weights. The advantage of this architecture over traditional weight based ones is simpler hardware implementation without multipliers or digital-analog converters (DACs). The name is derived due to similarity in the learning rule with an earlier architecture called Tempotron. We present simulations of memory capacity of the DELTRON for different random spatio-temporal spike patterns and also present SPICE simulation results of the core circuits involved in a reconfigurable mixed signal implementation of this architecture. {\textcopyright} 2012 IEEE.",

author = "Shaista Hussain and Arindam Basu and Mark Wang and Hamilton, \{Tara Julia\}",

note = "Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].; 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 ; Conference date: 02-12-2012 Through 05-12-2012",

year = "2012",

doi = "10.1109/APCCAS.2012.6419032",

language = "English",

isbn = "9781457717291",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "304--307",

booktitle = "2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012",

}

Hussain, S, Basu, A, Wang, M & Hamilton, TJ 2012, DELTRON: Neuromorphic architectures for delay based learning. in 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012., 6419032, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 304-307, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, Taiwan, China, 2/12/12. https://doi.org/10.1109/APCCAS.2012.6419032

DELTRON: Neuromorphic architectures for delay based learning. / Hussain, Shaista; Basu, Arindam; Wang, Mark et al.
2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. 2012. p. 304-307 6419032 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - DELTRON

T2 - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012

AU - Hussain, Shaista

AU - Basu, Arindam

AU - Wang, Mark

AU - Hamilton, Tara Julia

N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

PY - 2012

Y1 - 2012

N2 - We present a neuromorphic spiking neural network, the DELTRON, that can remember and store patterns by changing the delays of every connection as opposed to modifying the weights. The advantage of this architecture over traditional weight based ones is simpler hardware implementation without multipliers or digital-analog converters (DACs). The name is derived due to similarity in the learning rule with an earlier architecture called Tempotron. We present simulations of memory capacity of the DELTRON for different random spatio-temporal spike patterns and also present SPICE simulation results of the core circuits involved in a reconfigurable mixed signal implementation of this architecture. © 2012 IEEE.

AB - We present a neuromorphic spiking neural network, the DELTRON, that can remember and store patterns by changing the delays of every connection as opposed to modifying the weights. The advantage of this architecture over traditional weight based ones is simpler hardware implementation without multipliers or digital-analog converters (DACs). The name is derived due to similarity in the learning rule with an earlier architecture called Tempotron. We present simulations of memory capacity of the DELTRON for different random spatio-temporal spike patterns and also present SPICE simulation results of the core circuits involved in a reconfigurable mixed signal implementation of this architecture. © 2012 IEEE.

UR - https://www.scopus.com/pages/publications/84874185723

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84874185723&origin=recordpage

U2 - 10.1109/APCCAS.2012.6419032

DO - 10.1109/APCCAS.2012.6419032

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9781457717291

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 304

EP - 307

BT - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012

Y2 - 2 December 2012 through 5 December 2012

ER -

DELTRON: Neuromorphic architectures for delay based learning

Abstract

Publication series

Conference

Bibliographical note

Access Output

Other Access Options

Permanent Link

Other Files and Links

Fingerprint

Cite this