Delay robustness of low-order systems under PID control

This paper concerns the delay margin achievable using PID controllers for linear time-invariant (LTI) systems subject to variable, unknown time delays. The basic issue under investigation addresses the question: What is the largest range of time delay so that there exists a single PID controller to stabilize the delay plants within the entire range? Delay margin is a fundamental measure of robust stabilization against uncertain time delays and poses a fundamental, longstanding problem that remains open except in simple, isolated cases. In this paper we develop explicit expressions of the exact delay margin and its upper bounds achievable by a PID controller for low-order delay systems, notably the first- and second-order unstable systems with unknown delay. The effect of nonminimum phase zeros is also examined. Our results herein should provide useful guidelines in tuning PID controllers and in particular, the fundamental limits of delay within which a PID controller may robustly stabilize the delay processes.