Decoupled double synchronous reference frame PLL for power converters control

Pedro Rodríguez, Josep Pou, Joan Bergas, J. Ignacio Candela, Rolando P. Burgos, Dushan Boroyevich

Research output: Journal Publications and ReviewsRGC 21 - Publication in refereed journalpeer-review

Abstract

This paper deals with a crucial aspect in the control of grid-connected power converters, i.e., the detection of the fundamental-frequency positive-sequence component of the utility voltage under unbalanced and distorted conditions. Specifically, it proposes a positive-sequence detector based on a new decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL), which completely eliminates the detection errors of conventional synchronous reference frame PLL's (SRF-PLL). This is achieved by transforming both positive- and negative-sequence components of the utility voltage into the double SRF, from which a decoupling network is developed in order to cleanly extract and separate the positive- and negative-sequence components. The resultant DDSRF-PLL conducts then to a fast, precise, and robust positive-sequence voltage detection even under unbalanced and distorted grid conditions. The paper presents a detailed description and derivation of the proposed detection method, together with an extensive evaluation using simulation and experimental results from a digital signal processor-based laboratory prototype in order to verify and validate the excellent performance achieved by the DDSRF-PLL. © 2007 IEEE.
Original languageEnglish
Pages (from-to)584-592
JournalIEEE Transactions on Power Electronics
Volume22
Issue number2
DOIs
Publication statusPublished - Mar 2007
Externally publishedYes

Bibliographical note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

Funding

Manuscript received November 29, 2005; revised June 19, 2006. This paper was presented at IEEE PESC’05, Recife, Brazil, June 12–16, 2005. This work was supported by the Ministerio de Ciencia y Tecnologia of Spain under Grant PR2006-0411, Project ENE2004-07881-C03-02, the Engineering Research Center Shared Facilities supported by the National Science Foundation under NSF Award EEC-9731677, and by the CPES Industry Partnership Program. Recommended for publication by Associate Editor F. Blaabjerg.

Research Keywords

  • Grid-connected converters
  • Phase locked loop (PLL)
  • Positive sequence signals detection
  • Synchronous reference frame (SRF)

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