Decomposition design theory and methodology for arbitrary-shaped switch boxes

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Original languageEnglish
Pages (from-to)373-384
Journal / PublicationIEEE Transactions on Computers
Issue number4
Publication statusPublished - Apr 2006
Externally publishedYes


We consider the optimal design problem for arbitrary-shaped switch box, (r1,...,rk)-SB in which ri terminals are located on side i for i = 1,...,k and programmable switches are joining pairs of terminals from different sides. Previous investigations on switch box designs mainly focused on regular switch boxes in which all sides have the same number of terminals. By allowing different numbers of terminals on different sides, irregular switch boxes are more general and flexible for applications such as customized FPGAs and reconfigurable interconnection networks. The optimal switch box design problem is to design a switch box satisfying the given shape and routing capacity specifications with the minimum number of switches. We present a decomposition design method for a wide range of irregular switch boxes. The main idea of our method is to model a routing requirement as a nonnegative integer vector satisfying a system of linear equations and then derive a decomposition theory of routing requirements based on the theory of systems of linear Diophantine equations. The decomposition theory makes it possible to construct a large irregular switch box by combining small switch boxes of fixed sizes. Specifically, we can design a family of hyperuniversal (universal) (wd + c)-SBs with Θ(w) switches, where d and c are constant vectors and w is a scalar. We illustrate the design method by designing a class of optimal hyperuniversal irregular 3-sided switch boxes and a class of optimal rectangular universal switch boxes. Experimental results on the rectangular universal switch boxes with the VPR router show that the optimal design of irregular switch boxes does pay off. © 2006 IEEE.

Research Area(s)

  • FPGA, Hyperuniversal, Reconfigurable interconnection network, Switch block, Switch box, Universal