Customizable elliptic curve cryptosystems

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

76 Scopus Citations
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Author(s)

Detail(s)

Original languageEnglish
Pages (from-to)1048-1059
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume13
Issue number9
Publication statusPublished - Sep 2005
Externally publishedYes

Abstract

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2 m), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz. © 2005 IEEE.

Research Area(s)

  • Field-programmable gate arrays (FPGAs), Parallel architectures, Public key cryptography, Security

Citation Format(s)

Customizable elliptic curve cryptosystems. / Cheung, Ray C. C.; Telle, Nicolas Jean-Baptiste; Luk, Wayne; Cheung, Peter Y.K.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 9, 09.2005, p. 1048-1059.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review