Control of implantation Area in Direct-Current Plasma Immersion Ion Implantation (DC-PIII)

In plasma immersion ion implantation of planar samples such as silicon wafers, the only important ions are the ones arriving at the top surface. This is true for PIII - Ion Cut as well as SPIMOX (separation by plasma implantation of oxygen). In fact, ions implanted into the other surfaces are undesirable as they reduce the efficiency of the power supply and plasma source as well as give rise to metallic contamination. We have demonstrated direct-current plasma immersion ion implantation (DC-PIII) by using a grounded grid to separate the vacuum chamber, and this technique is excellent for planar sample implantation. The advantages include lower equipment cost, higher power and time efficiency, larger impact energy, and last but not least, the ability to perform high-energy implantation in a samll vacuum chamber. In this paper, we present our work on the control of the implantation area by adjusting the radius of the extraction hole, the distance between the conducting grid and the sample, and the radius of the wafer stage. The simulation is conducted using particle-in-cell (PIC) simulation and the results are checked by experiments. Our results indicate that the implanted area increases with the radius of the extraction hole and wafer stage, but decreases with a larger distance between the grid and sample. The effects of the extraction hole radius are the largest, followed by the placement of the conducting grid. The wafer stage poses the least influence. According to our simulation and experimental results, there is an optimal range of ratios of these parameters for each wafer size.