TY - GEN
T1 - Constructing High-rate Scale-free LDPC Codes
AU - Zheng, X.
AU - Lau, F. C. M.
AU - Tse, C. K.
PY - 2010/5
Y1 - 2010/5
N2 - Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the "pure" SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes. ©2010 IEEE.
AB - Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the "pure" SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes. ©2010 IEEE.
UR - https://www.scopus.com/pages/publications/77955993328
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-77955993328&origin=recordpage
U2 - 10.1109/ISCAS.2010.5537734
DO - 10.1109/ISCAS.2010.5537734
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 3781
EP - 3784
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010)
Y2 - 30 May 2010 through 2 June 2010
ER -