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Abstract
Speculative execution attacks are serious security problems that cause information leakage in computer systems by building speculative covert channels. Hardware defenses mitigate speculative covert channels through microarchitectural changes. However, two main limitations become the major bottleneck in existing hardware defenses. High-security hardware defenses, such as eager delay, can effectively mitigate both known and unknown covert channels. However, these defenses incur high performance overhead due to the long-fixed delayed execution applied in all potential attack scenarios. In contrast, hardware defenses with low performance overhead are faster and can mitigate known covert channels, but lack sufficient security to mitigate unknown covert channels. The limitations indicate that it is difficult to achieve better security and performance of a processor against speculative execution attacks using a single defense method. In this paper, we propose ConBOOM, a configurable central processing unit (CPU) microarchitecture that provides optimized switchable hardware defensive modes, including the high-security eager delay mode and two proposed performance-optimized modes based on the anticipated attack scenarios. The defensive modes allow for flexibility in mitigating different speculative execution attacks with better performance, unlike the existing defenses having fixed performance overhead for all attack scenarios. The ConBOOM modes can be switched without modifying the hardware, and switching ConBOOM to the suitable mode for the anticipated attack scenario is achieved through the provided software configuration interface. We implemented ConBOOM on Berkeley’s RISC-V out-of-order processor core (SonicBOOM). Furthermore, we evaluated ConBOOM on the VCU118 FPGA platform. Compared to the existing representative work with the fixed performance overhead of 39.1%, ConBOOM has the lower performance overhead ranging between 15.1% and 39.1% to mitigate different attack scenarios. ConBOOM provides more defensive flexibility with negligible hardware resource overhead about 2.0% and good security. © 2025 by the authors.
| Original language | English |
|---|---|
| Article number | 850 |
| Journal | Electronics (Switzerland) |
| Volume | 14 |
| Issue number | 5 |
| Online published | 21 Feb 2025 |
| DOIs | |
| Publication status | Published - Mar 2025 |
Funding
This research was supported by the Hong Kong Innovation and Technology Commission (ITF Seed Fund ITS/098/22), the City University of Hong Kong (Project Grant No. 9440356), and the Hong Kong Innovation and Technology Commission (InnoHK Project CIMDA).
Research Keywords
- configurable microarchitecture
- covert channels
- hardware defenses
- RISC-V
- speculative execution attacks
Publisher's Copyright Statement
- This full text is made available under CC-BY-NC 4.0. https://creativecommons.org/licenses/by-nc/4.0/
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ITF: Post-Quantum Resistant RISC-V Computing Platform
CHEUNG, C. C. R. (Principal Investigator / Project Coordinator)
1/12/23 → …
Project: Research