Computation and data transfer co-scheduling for interconnection bus minimization

C Q Xu; C.J. Xue; B.C. Hu; E. H. M. Sha

doi:10.1109/ASPDAC.2009.4796499

Computation and data transfer co-scheduling for interconnection bus minimization

C Q Xu
, C.J. Xue
, B.C. Hu
, E. H. M. Sha

Department of Computer Science

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

2 Citations (Scopus)

Abstract

High Instruction-Level-Parallelism in DSP and media applications demands highly clustered architecture. It is challenge to design an efficient, flexible yet cost saving interconnection network to satisfy the rapid increasing inter-cluster data transfer needs. This paper presents a computation and data transfer co-scheduling technique to minimize the number of partially connected interconnection buses required for a given embedded application while minimizing its schedule length. Previous researches in this area focused on scheduling computations to minimize the number of inter-cluster data transfers. The proposed co-scheduling technique in this paper not only schedules computations to reduce the number of inter-cluster data transfers, but also schedules inter- cluster data transfers to minimize the number of required partially connected buses for inter-cluster connection network. Experimental results indicate that 39.4% fewer buses required compared to current best known technique while achieving the same schedule length minimization. © 2009 IEEE.

Original language	English
Title of host publication	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Pages	311-316
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796499
Publication status	Published - 2009
Event	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan Duration: 19 Jan 2009 → 22 Jan 2009

Conference

Conference	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Place	Japan
City	Yokohama
Period	19/01/09 → 22/01/09

Research Keywords

Cluster tools
digital signal processing chips
field buses
processor scheduling
scheduling
DSP
computation
data transfer co-scheduling
high instruction-level-parallelism
inter-cluster connection network
inter-cluster data transfers
partially connected interconnection buses
schedule length minimization
Clustered Processors
Data Path Synthesis
Interconnection Network
Scheduling

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10.1109/ASPDAC.2009.4796499

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@inproceedings{1138d59fcd174b91a23a208730276da8,

title = "Computation and data transfer co-scheduling for interconnection bus minimization",

abstract = "High Instruction-Level-Parallelism in DSP and media applications demands highly clustered architecture. It is challenge to design an efficient, flexible yet cost saving interconnection network to satisfy the rapid increasing inter-cluster data transfer needs. This paper presents a computation and data transfer co-scheduling technique to minimize the number of partially connected interconnection buses required for a given embedded application while minimizing its schedule length. Previous researches in this area focused on scheduling computations to minimize the number of inter-cluster data transfers. The proposed co-scheduling technique in this paper not only schedules computations to reduce the number of inter-cluster data transfers, but also schedules inter- cluster data transfers to minimize the number of required partially connected buses for inter-cluster connection network. Experimental results indicate that 39.4\% fewer buses required compared to current best known technique while achieving the same schedule length minimization. {\textcopyright} 2009 IEEE.",

keywords = "Cluster tools, digital signal processing chips, field buses, processor scheduling, scheduling, DSP, computation, data transfer co-scheduling, high instruction-level-parallelism, inter-cluster connection network, inter-cluster data transfers, partially connected interconnection buses, schedule length minimization, Clustered Processors, Data Path Synthesis, Interconnection Network, Scheduling",

author = "Xu, \{C Q\} and C.J. Xue and B.C. Hu and Sha, \{E. H. M.\}",

year = "2009",

doi = "10.1109/ASPDAC.2009.4796499",

language = "English",

isbn = "9781424427482",

pages = "311--316",

booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

note = "Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 ; Conference date: 19-01-2009 Through 22-01-2009",

}

Xu, CQ, Xue, CJ, Hu, BC & Sha, EHM 2009, Computation and data transfer co-scheduling for interconnection bus minimization. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4796499, pp. 311-316, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 19/01/09. https://doi.org/10.1109/ASPDAC.2009.4796499

Computation and data transfer co-scheduling for interconnection bus minimization. / Xu, C Q; Xue, C.J.; Hu, B.C. et al.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2009. p. 311-316 4796499.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - Computation and data transfer co-scheduling for interconnection bus minimization

AU - Xu, C Q

AU - Xue, C.J.

AU - Hu, B.C.

AU - Sha, E. H. M.

PY - 2009

Y1 - 2009

N2 - High Instruction-Level-Parallelism in DSP and media applications demands highly clustered architecture. It is challenge to design an efficient, flexible yet cost saving interconnection network to satisfy the rapid increasing inter-cluster data transfer needs. This paper presents a computation and data transfer co-scheduling technique to minimize the number of partially connected interconnection buses required for a given embedded application while minimizing its schedule length. Previous researches in this area focused on scheduling computations to minimize the number of inter-cluster data transfers. The proposed co-scheduling technique in this paper not only schedules computations to reduce the number of inter-cluster data transfers, but also schedules inter- cluster data transfers to minimize the number of required partially connected buses for inter-cluster connection network. Experimental results indicate that 39.4% fewer buses required compared to current best known technique while achieving the same schedule length minimization. © 2009 IEEE.

AB - High Instruction-Level-Parallelism in DSP and media applications demands highly clustered architecture. It is challenge to design an efficient, flexible yet cost saving interconnection network to satisfy the rapid increasing inter-cluster data transfer needs. This paper presents a computation and data transfer co-scheduling technique to minimize the number of partially connected interconnection buses required for a given embedded application while minimizing its schedule length. Previous researches in this area focused on scheduling computations to minimize the number of inter-cluster data transfers. The proposed co-scheduling technique in this paper not only schedules computations to reduce the number of inter-cluster data transfers, but also schedules inter- cluster data transfers to minimize the number of required partially connected buses for inter-cluster connection network. Experimental results indicate that 39.4% fewer buses required compared to current best known technique while achieving the same schedule length minimization. © 2009 IEEE.

KW - Cluster tools

KW - digital signal processing chips

KW - field buses

KW - processor scheduling

KW - scheduling

KW - DSP

KW - computation

KW - data transfer co-scheduling

KW - high instruction-level-parallelism

KW - inter-cluster connection network

KW - inter-cluster data transfers

KW - partially connected interconnection buses

KW - schedule length minimization

KW - Clustered Processors

KW - Data Path Synthesis

KW - Interconnection Network

KW - Scheduling

U2 - 10.1109/ASPDAC.2009.4796499

DO - 10.1109/ASPDAC.2009.4796499

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9781424427482

SP - 311

EP - 316

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

T2 - Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009

Y2 - 19 January 2009 through 22 January 2009

ER -

Computation and data transfer co-scheduling for interconnection bus minimization

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Research Keywords

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