Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Author(s)

  • Qingan Li
  • Jianhua Li
  • Liang Shi
  • Mengying Zhao
  • Yanxiang He

Related Research Unit(s)

Detail(s)

Original languageEnglish
Article number6588311
Pages (from-to)1829-1840
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number8
Online published30 Aug 2013
Publication statusPublished - Aug 2014

Abstract

Hybrid caches consisting of static RAM (SRAM) and spin-torque transfer (STT)-RAM have been proposed recently for energy efficiency. To explore the advantages of hybrid cache, most of the management strategies for hybrid caches employ migration-based techniques to dynamically move write-intensive data from STT-RAM to SRAM. These techniques involve additional access operations, and thus lead to extra overheads. In this paper, we propose two compilation-based approaches to improve the energy efficiency and performance of STT-RAM-based hybrid cache by reducing the migration overheads. The first approach, migration-aware data layout, is proposed to reduce the migrations by rearranging the data layout. The second approach, migration-aware cache locking, is proposed to reduce the migrations by locking migration-intensive memory blocks into SRAM part of hybrid cache. Furthermore, experiments show that these two methods can be combined to reduce more migrations. The reduction of migration overheads can improve the energy efficiency and performance of STT-RAM-based hybrid cache. Experimental results show that, combining these two methods, on average, the number of write operations on STT-RAM is reduced by 17.6%, the number of migrations is reduced by 38.9%, the total dynamic energy is reduced by 15.6%, and the total access latency is reduced by 13.8%. © 1993-2012 IEEE.

Research Area(s)

  • Cache, compiler, hybrid cache, NVM, spin-torque transfer (STT)-RAM.

Citation Format(s)

Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems. / Li, Qingan; Li, Jianhua; Shi, Liang; Zhao, Mengying; Xue, Chun Jason; He, Yanxiang.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 8, 6588311, 08.2014, p. 1829-1840.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review