Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
| Original language | English |
|---|---|
| Title of host publication | 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) |
| Pages | 273-278 |
| Publication status | Published - Jan 2013 |
Conference
| Title | 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) |
|---|---|
| Place | Japan |
| City | Yokohama |
| Period | 22 - 25 January 2013 |
Link(s)
Abstract
Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.
Citation Format(s)
Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache. / Li, Qingan; Li, Jianhua; Shi, Liang et al.
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC). 2013. p. 273-278 6509608.
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC). 2013. p. 273-278 6509608.
Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review
