Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

Qingan Li; Jianhua Li; Liang Shi; Chun Jason Xue; Yiran Chen; Yanxiang He

doi:10.1109/ASPDAC.2013.6509608

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

Qingan Li
, Jianhua Li
, Liang Shi
, Chun Jason Xue
, Yiran Chen
, Yanxiang He

Department of Computer Science

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

18 Citations (Scopus)

Abstract

Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

Original language	English
Title of host publication	2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)
Pages	273-278
DOIs	https://doi.org/10.1109/ASPDAC.2013.6509608
Publication status	Published - Jan 2013
Event	18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) - Yokohama, Japan Duration: 22 Jan 2013 → 25 Jan 2013

Conference

Conference	18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013)
Place	Japan
City	Yokohama
Period	22/01/13 → 25/01/13

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@inproceedings{65ebfd2578324887b610595b797af656,

title = "Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache",

abstract = "Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3\%, and reduce the dynamic energy consumption by 27.6\%.",

author = "Qingan Li and Jianhua Li and Liang Shi and Xue, \{Chun Jason\} and Yiran Chen and Yanxiang He",

year = "2013",

month = jan,

doi = "10.1109/ASPDAC.2013.6509608",

language = "English",

isbn = "9781467330299",

pages = "273--278",

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note = "18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) ; Conference date: 22-01-2013 Through 25-01-2013",

}

TY - GEN

T1 - Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

AU - Li, Qingan

AU - Li, Jianhua

AU - Shi, Liang

AU - Xue, Chun Jason

AU - Chen, Yiran

AU - He, Yanxiang

PY - 2013/1

Y1 - 2013/1

N2 - Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

AB - Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed. However, refresh operations consume additional energy. In this paper, we propose to reduce the number of refresh operations through re-arranging program data layout at compilation time. An N-refresh scheme is also proposed. Experimental results show that, on average, the proposedmethods can reduce the number of refresh operations by 73.3%, and reduce the dynamic energy consumption by 27.6%.

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U2 - 10.1109/ASPDAC.2013.6509608

DO - 10.1109/ASPDAC.2013.6509608

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9781467330299

SN - 9781467330305

SP - 273

EP - 278

BT - 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

T2 - 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013)

Y2 - 22 January 2013 through 25 January 2013

ER -

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

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