Combined successive and σ-δ A/D conversion scheme

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)

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Author(s)

Detail(s)

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1294-1297
Volume2
ISBN (Print)780312813
Publication statusPublished - 1993
Externally publishedYes

Publication series

Name
Volume2
ISSN (Electronic)0271-4310

Conference

TitleProceedings of the 1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period3 - 6 May 1993

Abstract

This paper presents a mismatch-insensitive approach to the multi-bit σ-δ modulator design. The multi-bit conversion is realised by successive approximation and a simple controlled averaging technique is introduced to cancel the first order mismatch error. The cost in circuit complexity increase is very modest.

Citation Format(s)

Combined successive and σ-δ A/D conversion scheme. / Ping, Li.

Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2 Publ by IEEE, 1993. p. 1294-1297.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with ISBN/ISSN)