Combined successive and σ-δ A/D conversion scheme

Li Ping

Combined successive and σ-δ A/D conversion scheme

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

1 Citation (Scopus)

Abstract

This paper presents a mismatch-insensitive approach to the multi-bit σ-δ modulator design. The multi-bit conversion is realised by successive approximation and a simple controlled averaging technique is introduced to cancel the first order mismatch error. The cost in circuit complexity increase is very modest.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
Pages	1294-1297
Volume	2
ISBN (Print)	780312813
Publication status	Published - 1993
Externally published	Yes
Event	Proceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Duration: 3 May 1993 → 6 May 1993

Publication series

Name
Volume	2
ISSN (Electronic)	0271-4310

Conference

Conference	Proceedings of the 1993 IEEE International Symposium on Circuits and Systems
City	Chicago, IL, USA
Period	3/05/93 → 6/05/93

Other Access Options

Check CityUHK Library

Permanent Link

Right click to copy link

Cite this

@inproceedings{8ac5cede428748909ae43411bf1e986f,

title = "Combined successive and σ-δ A/D conversion scheme",

abstract = "This paper presents a mismatch-insensitive approach to the multi-bit σ-δ modulator design. The multi-bit conversion is realised by successive approximation and a simple controlled averaging technique is introduced to cancel the first order mismatch error. The cost in circuit complexity increase is very modest.",

author = "Li Ping",

year = "1993",

language = "English",

isbn = "780312813",

volume = "2",

publisher = "IEEE",

pages = "1294--1297",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

address = "United States",

note = "Proceedings of the 1993 IEEE International Symposium on Circuits and Systems ; Conference date: 03-05-1993 Through 06-05-1993",

}

TY - GEN

T1 - Combined successive and σ-δ A/D conversion scheme

AU - Ping, Li

PY - 1993

Y1 - 1993

N2 - This paper presents a mismatch-insensitive approach to the multi-bit σ-δ modulator design. The multi-bit conversion is realised by successive approximation and a simple controlled averaging technique is introduced to cancel the first order mismatch error. The cost in circuit complexity increase is very modest.

AB - This paper presents a mismatch-insensitive approach to the multi-bit σ-δ modulator design. The multi-bit conversion is realised by successive approximation and a simple controlled averaging technique is introduced to cancel the first order mismatch error. The cost in circuit complexity increase is very modest.

UR - http://www.scopus.com/inward/record.url?scp=0027204513&partnerID=8YFLogxK

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-0027204513&origin=recordpage

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 780312813

VL - 2

SP - 1294

EP - 1297

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - IEEE

T2 - Proceedings of the 1993 IEEE International Symposium on Circuits and Systems

Y2 - 3 May 1993 through 6 May 1993

ER -

Combined successive and σ-δ A/D conversion scheme

Abstract

Publication series

Conference

Other Access Options

Permanent Link

Other Files and Links

Fingerprint

Cite this