Code motion for migration minimization in STT-RAM based hybrid cache

Qingan Li; Liang Shi; Jianhua Li; Chun Jason Xue; Yanxiang He

doi:10.1109/ISVLSI.2012.84

Code motion for migration minimization in STT-RAM based hybrid cache

Qingan Li
, Liang Shi
, Jianhua Li
, Chun Jason Xue
, Yanxiang He

City University of Hong Kong

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

6 Citations (Scopus)

Abstract

Hybrid caches consisting of both STT-RAM andSRAM have been proposed recently for energy efficiency. Toexplore the advantages of hybrid cache, most work on hybridcaches employs migration based strategies to dynamically movewrite-intensive data from STT-RAM to SRAM. Migrations requireadditional read and write operations for data movementand may lead to significant overheads. To address this issue,this paper proposes a compilation method, Migration-awareCode Motion (MCM), to improve the energy efficiency andperformance of STT-RAM based hybrid cache. This methodis designed to change the data access patterns in memoryblocks such that the migration overhead is reduced without anyhardware modification. The experimental results show that theproposed method can reduce the number of migrations by 10.6%,reduce the dynamic energy by 6.2%, and reduce the total latency by 5.3% on average. © 2012 IEEE.

Original language	English
Title of host publication	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages	410-415
DOIs	https://doi.org/10.1109/ISVLSI.2012.84
Publication status	Published - 2012
Event	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States Duration: 19 Aug 2012 → 21 Aug 2012

Conference

Conference	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Place	United States
City	Amherst, MA
Period	19/08/12 → 21/08/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/ISVLSI.2012.84

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@inproceedings{690bac656c834594a225c1d5bf0bb2d5,

title = "Code motion for migration minimization in STT-RAM based hybrid cache",

abstract = "Hybrid caches consisting of both STT-RAM andSRAM have been proposed recently for energy efficiency. Toexplore the advantages of hybrid cache, most work on hybridcaches employs migration based strategies to dynamically movewrite-intensive data from STT-RAM to SRAM. Migrations requireadditional read and write operations for data movementand may lead to significant overheads. To address this issue,this paper proposes a compilation method, Migration-awareCode Motion (MCM), to improve the energy efficiency andperformance of STT-RAM based hybrid cache. This methodis designed to change the data access patterns in memoryblocks such that the migration overhead is reduced without anyhardware modification. The experimental results show that theproposed method can reduce the number of migrations by 10.6\%,reduce the dynamic energy by 6.2\%, and reduce the total latency by 5.3\% on average. {\textcopyright} 2012 IEEE.",

author = "Qingan Li and Liang Shi and Jianhua Li and Xue, \{Chun Jason\} and Yanxiang He",

year = "2012",

doi = "10.1109/ISVLSI.2012.84",

language = "English",

isbn = "9780769547671",

pages = "410--415",

booktitle = "Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012",

note = "2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 ; Conference date: 19-08-2012 Through 21-08-2012",

}

Code motion for migration minimization in STT-RAM based hybrid cache. / Li, Qingan; Shi, Liang; Li, Jianhua et al.
Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. p. 410-415 6296508.

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - Code motion for migration minimization in STT-RAM based hybrid cache

AU - Li, Qingan

AU - Shi, Liang

AU - Li, Jianhua

AU - Xue, Chun Jason

AU - He, Yanxiang

PY - 2012

Y1 - 2012

N2 - Hybrid caches consisting of both STT-RAM andSRAM have been proposed recently for energy efficiency. Toexplore the advantages of hybrid cache, most work on hybridcaches employs migration based strategies to dynamically movewrite-intensive data from STT-RAM to SRAM. Migrations requireadditional read and write operations for data movementand may lead to significant overheads. To address this issue,this paper proposes a compilation method, Migration-awareCode Motion (MCM), to improve the energy efficiency andperformance of STT-RAM based hybrid cache. This methodis designed to change the data access patterns in memoryblocks such that the migration overhead is reduced without anyhardware modification. The experimental results show that theproposed method can reduce the number of migrations by 10.6%,reduce the dynamic energy by 6.2%, and reduce the total latency by 5.3% on average. © 2012 IEEE.

AB - Hybrid caches consisting of both STT-RAM andSRAM have been proposed recently for energy efficiency. Toexplore the advantages of hybrid cache, most work on hybridcaches employs migration based strategies to dynamically movewrite-intensive data from STT-RAM to SRAM. Migrations requireadditional read and write operations for data movementand may lead to significant overheads. To address this issue,this paper proposes a compilation method, Migration-awareCode Motion (MCM), to improve the energy efficiency andperformance of STT-RAM based hybrid cache. This methodis designed to change the data access patterns in memoryblocks such that the migration overhead is reduced without anyhardware modification. The experimental results show that theproposed method can reduce the number of migrations by 10.6%,reduce the dynamic energy by 6.2%, and reduce the total latency by 5.3% on average. © 2012 IEEE.

UR - https://www.scopus.com/pages/publications/84867792750

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84867792750&origin=recordpage

U2 - 10.1109/ISVLSI.2012.84

DO - 10.1109/ISVLSI.2012.84

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9780769547671

SP - 410

EP - 415

BT - Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

T2 - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Y2 - 19 August 2012 through 21 August 2012

ER -

Code motion for migration minimization in STT-RAM based hybrid cache

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